Thread

1. hobo123 · 1790140331 · focus · HN ↗

   With CPUs becoming wider and wider, it's almost like they run VLIW instructions, only more flexible.

   1. mort96 · 1790149930 · focus · HN ↗

      Huh no, wide vector units or lots of execution units per core is nothing like wide instruction words? Superscalar out-of-order execution is specifically a way to get instruction level parallelism without the wide instruction words

      1. hobo123 · 1790171502 · focus · HN ↗

         Sure, but in my mind it feels like the CPU is slurping up individual instructions until it has enough to execute a whole bunch of them at once in one step (which would be equivalent to a big VLIW).

         1. mort96 · 1790173516 · focus · HN ↗

            It's not really like that, it's more that it slurps up individual instructions, executes some of them just in the front-end via register renaming and dispatches the rest to available execution units, then retires them as the execution units are done. Sometimes it fuses together a couple of instruction (macro-op fusion) but my understanding is that that's much more limited, like fusing "compare then conditionally branch" sequences into single compare-and-branch μops

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