Huh no, wide vector units or lots of execution units per core is nothing like wide instruction words? Superscalar out-of-order execution is specifically a way to get instruction level parallelism without the wide instruction words
I was thinking that for this new generation, "Superscalar" doesn't cover it anymore, except as a generic term for the design technique. "Ultrascalar"? "Superscalar Pro"?
I mean superscalar just is a different name for using wide cores and runtime dependency tracking and out-of-order execution for instruction level parallelism without VLIW.
To my eyes, your message looks kinda like, "The term 'bicycle' doesn't cover it anymore, things have changed so much since they were introduced. We should call them something else, maybe 'bicycle pro'? 'super bicycle'?" No it's just a bike, and no, modern CPUs are just CPUs which look scalar at the ISA level but have ILP
Sure, but in my mind it feels like the CPU is slurping up individual instructions until it has enough to execute a whole bunch of them at once in one step (which would be equivalent to a big VLIW).
It's not really like that, it's more that it slurps up individual instructions, executes some of them just in the front-end via register renaming and dispatches the rest to available execution units, then retires them as the execution units are done. Sometimes it fuses together a couple of instruction (macro-op fusion) but my understanding is that that's much more limited, like fusing "compare then conditionally branch" sequences into single compare-and-branch μops
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To my eyes, your message looks kinda like, "The term 'bicycle' doesn't cover it anymore, things have changed so much since they were introduced. We should call them something else, maybe 'bicycle pro'? 'super bicycle'?" No it's just a bike, and no, modern CPUs are just CPUs which look scalar at the ISA level but have ILP
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