Thread

1. dagmx · 1789712627 · focus · HN ↗

   For reference , Fex is a translation framework for x86 to ARM much like Apple’s Rosetta2 and Microsoft’s Prism.

   Valve sponsor development as it’s also the way the new Steam Frame supports x86 games. It’s also being used (as a fork) in Crossover Beta to replace the use of Rosetta2.

   1. MiroslavPokorny · 1789717515 · focus · HN ↗

      Why doesnt Stream require their binaries to be compiled to some bytecode and transpiled during the install ?

      THen they wouldnt require any emulator for any new compiles.

      1. raverbashing · 1789721801 · focus · HN ↗

         They do

         x86 bytecode is bytecode

         1. DonHopkins · 1789722179 · focus · HN ↗

            that bites
         2. ErroneousBosh · 1789725164 · focus · HN ↗

            I mean don't modern CPUs basically just run an x86_64 emulator on a RISC machine anyway? Like there's a layer between the microcode and the actual x86 instructions already.

            1. raverbashing · 1789725804 · focus · HN ↗

               I think it's more like a (kinda) VLIW machine but yes, pretty much

               1. MiroslavPokorny · 1789819365 · focus · HN ↗

                  VLIW implies packets of different independent instructions that can be executed in parallel. I dont think this definition is ever true for the vast majority of x86 instructions.
            2. sph · 1789730490 · focus · HN ↗

               Yes, but the “architecture-independent” bytecode for these RISC machines that run underneath your various Intel and AMD CPU models is the x86_64 instruction set.
            3. adwn · 1789730506 · focus · HN ↗

               No, that's a myth. It's true that the instruction decoder in a CPU core translates from ISA opcodes to micro-ops for the backend, but those micro-ops are in many cases functionally very close to the ISA instruction and decidedly not RISC-like. For example, the ADD r/m64, imm32 instruction (read from memory, add constant, write to memory) is translated to a single micro-op on several Zen architectures [1], which is far from anything you could call "RISC".

               [1] <a href="https:&#x2F;&#x2F;uops.info&#x2F;html-instr&#x2F;ADD_M64_I32.html" rel="nofollow">https:&#x2F;&#x2F;uops.info&#x2F;html-instr&#x2F;ADD_M64_I32.html

            4. jcranmer · 1789737974 · focus · HN ↗

               No, they don&#x27;t. x86 is a superscalar processor, and it does what all superscalar processors do--translate the instructions into µops for execution and dispatch to the various execution units, with the µops not being 1-1 with the original instructions. However, it was supposed to be impossible for a CISC architecture to be superscalar, so this is what spawns the myth that it&#x27;s somehow cheating by executing a RISC architecture under the hood.

               1. ErroneousBosh · 1789762679 · focus · HN ↗

                  Thanks, I didn&#x27;t know that and now I do.
            5. MiroslavPokorny · 1789786391 · focus · HN ↗

               Reality is very different.

               The fact that x86 is not RISC, it contains many instructions which support memory as the source and destination or both, something which is often an advantage in terms of code density, and speed.

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