Thread

1. aurareturn · 1789540438 · focus · HN ↗

   Chip density increase is slowing down. Since N10, density scaling has been 60-80%. N3 to N2 is only 20%. And now N2 to A14 is also only 20%.

   1. georgeburdell · 1789576801 · focus · HN ↗

      A lot of that is the lack of SRAM scaling. There’s still quite a bit of improvements in the back end (metal traces). That aside, if foundries adopted say a 1T-1C SRAM we’d see a pretty rapid density doubling

      1. tliltocatl · 1789677230 · focus · HN ↗

         > 1T-1C SRAM

         Aka eDRAM? It was a thing back on 14nm node, but AFAIR not so much anymore. The 1C part is hard to get right in a way that is compatible with a logic process.

         1. to11mtm · 1789683941 · focus · HN ↗

            It gets confusing...

            eDRAM isn't the same as 1T-SRAM, which isn't quite the same as 1T-1C SRAM...

            But overall they run into the same problems that you mention; it's just too hard to get a capacitor in play.

            There is Zeno Semi's Bi-SRAM, buuuut it hasn't seemed to catch on for one reason or another.

            1. tliltocatl · 1789725456 · focus · HN ↗

               > Bi-SRAM

               Looks cool, but isn't it by definition planar process-only, no FinFET for you?

               1. to11mtm · 1789861899 · focus · HN ↗

                  I'll admit I am not well versed on this subject on any measure, but there is this [0] paper indicating FinFET is doable, although IDK if there's any sort of hand-waving or other limitations involved.

                  [0] - <a href="https:&#x2F;&#x2F;ieeexplore.ieee.org&#x2F;document&#x2F;8614555" rel="nofollow">https:&#x2F;&#x2F;ieeexplore.ieee.org&#x2F;document&#x2F;8614555

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