A lot of that is the lack of SRAM scaling. There’s still quite a bit of improvements in the back end (metal traces). That aside, if foundries adopted say a 1T-1C SRAM we’d see a pretty rapid density doubling
Is 1T1C SRAM a technological thing or does it mean "persuade designers to use DRAM in the many cases where the retention contract could be timeboxed with a bit of extra thought and cross-team haggling"?
MRAM is 1T, non-volatile and supposedly has nanosecond-scale write times so it naively seems like it'd be an ideal SRAM replacement. But I guess shrinking MTJ is more difficult than other components or there are some other limitations.
Aka eDRAM? It was a thing back on 14nm node, but AFAIR not so much anymore. The 1C part is hard to get right in a way that is compatible with a logic process.
I'll admit I am not well versed on this subject on any measure, but there is this [0] paper indicating FinFET is doable, although IDK if there's any sort of hand-waving or other limitations involved.
The reality is often going to be much worse than TSMC's N2 -> A14 "mixed design" 20% density increase marketing spin.
Apparently the N2 -> A14 density increase for logic is 23% (Tom's Hardware), and about 0% for both SRAM and analog.
Both CPUs and GPUs devote considerable space to SRAM (registers & cache), and are 50% or less logic, so for them the density increase will be more like 10% rather than TSMC's 20% marketing number.
aurareturn · · focus · HN ↗
georgeburdell · · focus · HN ↗
smallmancontrov · · focus · HN ↗
the8472 · · focus · HN ↗
georgeburdell · · focus · HN ↗
tliltocatl · · focus · HN ↗
Aka eDRAM? It was a thing back on 14nm node, but AFAIR not so much anymore. The 1C part is hard to get right in a way that is compatible with a logic process.
to11mtm · · focus · HN ↗
eDRAM isn't the same as 1T-SRAM, which isn't quite the same as 1T-1C SRAM...
But overall they run into the same problems that you mention; it's just too hard to get a capacitor in play.
There is Zeno Semi's Bi-SRAM, buuuut it hasn't seemed to catch on for one reason or another.
tliltocatl · · focus · HN ↗
Looks cool, but isn't it by definition planar process-only, no FinFET for you?
to11mtm · · focus · HN ↗
[0] - <a href="https://ieeexplore.ieee.org/document/8614555" rel="nofollow">https://ieeexplore.ieee.org/document/8614555
HarHarVeryFunny · · focus · HN ↗
Apparently the N2 -> A14 density increase for logic is 23% (Tom's Hardware), and about 0% for both SRAM and analog.
Both CPUs and GPUs devote considerable space to SRAM (registers & cache), and are 50% or less logic, so for them the density increase will be more like 10% rather than TSMC's 20% marketing number.