It's hard to tell because AI has pushed up costs. IE. Chip fab margins are increasing.
But generally, I think it's even or increasing $/transistor for each node. I'd guess that A14 would have been 20% more expensive than N2 regardless or AI or not.
It probably is still worth it because you're also getting 20-30% better power efficiency - which is a big deal for data center chips.
If we exclude short-term shortages then no. The cost to make a wafer hasn't really changed. Larger wafers improved costs but that's about it AFAIK.
Feature sizes have been shrinking unevenly for two decades now combined with the overall slowdown in improvements. Transistors themselves are FinFET geometry and something like 15-30 atoms thick and maybe 80-100 across. There ain't much juice left to squeeze in terms of size but perhaps we'll figure out how to reduce leakage (heat).
Physics hates the very large and the very small. The large get the tyranny of volume scaling + general relativity. The small have their entire concept of reality smashed by quantum mechanics.
I'm saying Fujitsu never made any real attempt to sell their product to anyone except very large companies with purchasing departments. Thus it is little wonder they never really got much in the way of sales.
Maybe that strategy works in Japan or Asia but it didn't work here and I think that's a shame because we could have used the competition.
The cost-per-transistor used to fall as density increased (Moore's Law), but has now basically flattened off.
As each generation of lithography tech (DUV -> EUV -> High-NA EUV) gets pushed to the limit, it becomes necessary to use multiple etching steps per layer (higher cost, less wafers-per-minute) where previously one had been enough, then the next generation (e.g. EUV vs DUV) resets that to one step, then that becomes two ...
The trouble is that each new generation of tech costs considerably more than the one it replaces, both in terms of machine cost and operational cost, so the overall trend seems to have become fairly flat.
aurareturn · · focus · HN ↗
osnium123 · · focus · HN ↗
aurareturn · · focus · HN ↗
But generally, I think it's even or increasing $/transistor for each node. I'd guess that A14 would have been 20% more expensive than N2 regardless or AI or not.
It probably is still worth it because you're also getting 20-30% better power efficiency - which is a big deal for data center chips.
xenadu02 · · focus · HN ↗
Feature sizes have been shrinking unevenly for two decades now combined with the overall slowdown in improvements. Transistors themselves are FinFET geometry and something like 15-30 atoms thick and maybe 80-100 across. There ain't much juice left to squeeze in terms of size but perhaps we'll figure out how to reduce leakage (heat).
Physics hates the very large and the very small. The large get the tyranny of volume scaling + general relativity. The small have their entire concept of reality smashed by quantum mechanics.
xenadu02 · · focus · HN ↗
Maybe that strategy works in Japan or Asia but it didn't work here and I think that's a shame because we could have used the competition.
HarHarVeryFunny · · focus · HN ↗
As each generation of lithography tech (DUV -> EUV -> High-NA EUV) gets pushed to the limit, it becomes necessary to use multiple etching steps per layer (higher cost, less wafers-per-minute) where previously one had been enough, then the next generation (e.g. EUV vs DUV) resets that to one step, then that becomes two ...
The trouble is that each new generation of tech costs considerably more than the one it replaces, both in terms of machine cost and operational cost, so the overall trend seems to have become fairly flat.
MichaelZuo · · focus · HN ↗