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1. librasteve · 1790970778 · focus · HN ↗

   As the video points out, there is a hardware&#x2F;software feedback loop at play here. Since the hardware is deeply pipelined SIMD FPU datapath, the software is hand tuned machine coded transformations. In addition to limiting flexibility (every variation has to be ground out in CUDA), this prevents sparse matrix type optimisations. I predict that a set of general purpose CPUs - non shared memory at this scale - would be a much better use of transistor&#x2F;power. And you can code that at high level give a CSP style approach such as <a href="https:&#x2F;&#x2F;bil-lang.org" rel="nofollow">https:&#x2F;&#x2F;bil-lang.org

   1. feffe · 1790979094 · focus · HN ↗

      I think tenstorrent architecture is more like this. A grid of RISC-V cores with local SRAM and vector units.

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