...you know, that reads somewhat like "The Case for Complex Instruction Set Computer". In fact, it straight up demolishes the very first of the core premises of the famous "Case for RISC" paper: that the memory speed has finally caught up with the CPU speed. Nope, it hasn't. The same goes for its "Code Density" argument: nope, code density is very important.
Then again, the original "Case for RISC" paper was misnamed; it's really "Case Against CISC": Patterson and Ditzel are very careful to never state what, exactly, do they mean by "RISC" they're supposedly advocating for, nor do they actually advocate for it — they mostly just criticize the current ISAs and the overall design approach to them.
Joker_vD · · focus · HN ↗
Then again, the original "Case for RISC" paper was misnamed; it's really "Case Against CISC": Patterson and Ditzel are very careful to never state what, exactly, do they mean by "RISC" they're supposedly advocating for, nor do they actually advocate for it — they mostly just criticize the current ISAs and the overall design approach to them.
pjmlp · · focus · HN ↗
throwawayk7h · · focus · HN ↗
renox · · focus · HN ↗
Sure, but ARM's thumb has shown that you can get a RISC which has the same code density as current CISCs.
Of course, it's because current CISCs are bad due to backward compatibility but..