Thread · HN Continuity

I don't know how much of a difference this makes in practice. Creating the photomasks and proving the resulting silicon is still the predominant bottleneck in chip design.

If you have a flaw in the RTL and need to do a respin it can add 3+ months to the lead time of a new product. Allowing GPT to iterate through this kind of cycle seems economically infeasible unless you have an enormous amount of spare EUV capacity (you don't).