Thread

GPT-Synopsys: Frontier Intelligence to Revolutionize Chip Design

189 points · 111 comments · giuliomagnifico

aurareturn · 1790859860 · focus · HN ↗
From an investment perspective, I think chip fabs TSMC, Intel, and Samsung will benefit from better AI chip design tools.
If AI made it 100x faster and cheaper to build software, you suddenly have an explosion of software that need to be hosted. So companies like AWS/iOS App Store/cloud companies benefit.
If AI makes designing chips 100x faster and cheaper, you will have an explosion of custom chips for all sorts of applications. These chips still need to be physically made at TSMC, Intel, or Samsung.
Apple says it takes 3-4 years to design each Apple Silicon generation.[0] So the M6 was being designed in 2022-2023 already. Reports are that it costs hundreds of millions to a billion to design a cutting edge chip from scratch to finish.[0]
The cool thing is that we'll have niche ASIC chips for accelerating special applications that previously didn't have big of a market for someone to make a profit on. This is the same thing with software today. It's much easier to build custom software for a small niche and be profitable today than in 2022.
Maybe some day, a kid in his garage can just tell an AI to design a custom chip, send it to TSMC, and get the chip in the mail in a few weeks.
And given that Moore's Law is essentially dead in terms of density scaling, having an AI to automatically optimize the hell out of design and squeeze as much performance as possible out of the transistors could help us have a few more years of nice performance increase.
[0]<a href="https://fireflies.ai/blog/johny-srouji-and-john-ternus-interview" rel="nofollow">https://fireflies.ai/blog/johny-srouji-and-john-ternus-inter...
[1]<a href="https://www.granitefirm.com/blog/us/2023/04/29/cost-of-chip-foundry/" rel="nofollow">https://www.granitefirm.com/blog/us/2023/04/29/cost-of-chip-...
1. kurthr · 1790866957 · focus · HN ↗
  This might make some sense if, the cost of any change in design vs requirement wouldn't cost $30-50M in mask and tape-out alone. That doesn't count the first wafer 'hot lots' just to get the design's first wafer out in only 3 months, or the bringup and modified test equipment to validate the design, or the corners testing and optimization, or the package tooling, or... Those can easily be additional $10Ms and that's per design, if you do a full mask change. If you can "fix it in metal", you might get that down to just $10M and 1 month?
  This isn't software. The time, labor, and equipment costs of the first wafer dwarf the redesign cost, so it makes sense to get it right the first time. What if every build, compile, and link cost you $10M and 1 month? How would that change your work flow?
  Most of the "AI" design tools today are focused on verification, validation and layout, which makes a lot of sense. They might help with architecture in the future (or making something high yield AND easy to fix in metal)?
  You could run a small design on an MPW shuttle to reduce these costs, but your TTM get's longer, the yields won't be as high, and if you go to mass production you still face the huge mask costs.
  Another place this might make some sense is reworking old large die 130nm designs on 8" wafers to be newer 28mm designs on 12", there are a LOT of those. The mask costs are lower, the design is well understood with lots of process margin, and wafer/yield costs could be modeled and favorable. Of course analog scaling is a whole separate kettle of fish.
  1. MisterMunchkin · 1790868878 · focus · HN ↗
    But then you are assuming the current way is optimal. Why can’t we have a 3d-printer-style contraption for chips?
    If people have millions of new chip designs that need making, perhaps that will be motivation to invent a new way of making chips. It might not be better at manufacturing a billion of the same chip, but maybe it’s better at producing a billion different chips. Then every HFT could have their own chip and people could try out all kinds of new designs without committing a fortune.
    kurthr · 1790870064 · focus · HN ↗
    Think how long it takes for a 3D printer to finish a single design with 0.1mm resolution. Now scale that down to 10nm. The time to complete goes up by 10^12. A 1 minute design would scale to 2M years.
    There's a reason e-beam lithography is only used to make masks, and why it's one of the most expensive parts of the manufacture.
    15155 · 1790871245 · focus · HN ↗
    E-beam lithography absolutely is/can be used to manufacture one-off chips.
    The problem isn't lithography, though, it's all of the adjacent processes (ion implantation and a dozen other things) that are fab/process-specific and require even more complicated/expensive equipment.
    Shuttle runs give you a true-to-process tapeout and are dirt cheap, so only universities and the like bother with direct-write.
    hn_acc1 · 1790887687 · focus · HN ↗
    Can 3D printers print with 1 micrometer (not millimeter) accuracy? 1 micron gets you things like the original 8086. Oh wait, current best desktop printers get like 100 micron (0.1 mm) accuracy. So scale up what we have now 100x in terms of accuracy (imagine how much bigger / more precise the motors, magnets, everything has to be). EASILY 10-50x the cost of a good home 3D printer today - say $50K. And 8086? Your phone is faster than probably 50-100 of them in parallel today) - so $100K (materials aren't cheap) to print a series of chips that were insanely obsolete 20 years ago and 1 $500 fpga could run circles around. Then scale that up at least another 50x to get semi-competitive (20 nm). There's a reason they put fabs in places like Arizona where there are relatively few earthquakes... Even the garbage truck driving past your house could damage your chip.
    As far as home printing stuff: the clean room requirements are INSANE: just the HF (hydrofluoric acid) is crazy bad stuff that you could NOT get certified for general consumer use, no way, no how. And even if you did, you'd be crazy to buy something that comes with HF as part of the process.. And that's just ONE bad, bad chemical used by TSMC all the time.
    FPGAs are the "faster-than-software / can make a custom chip" compromise - companies like Intel used to (not sure if they still do) use a ton of FGPAs to simulate new chip designs. Precisely because manufacturing state-of-the-art chips is so hard.
    dadoum · 1790899873 · focus · HN ↗
    There are actually desktop SLA printers with 1~10µm of accuracy, but as you said the website does not show a buy button, just a Request quote button.
    vlovich123 · 1790905283 · focus · HN ↗
    We do have a ton of capacity at trailing nodes from 28nm to 180nm where you can pump something out in 4-5 months after tape-out. Of course, it's still a lot of work and the initial prototype will cost you anywhere from 5-20k (180nm) to 60-150k (28nm) depending on the size of the chip. A dedicated wafer will run ~1-2M at 28nm and 100-200k for 180nm.
    But yeah, home custom chip design isn't practical and custom PCBs aren't worth it because they're super cheap, fast and cost pennies.
2. maeln · 1790868828 · focus · HN ↗
  > These chips still need to be physically made at TSMC, Intel, or Samsung.
  That's for the most advance tech (sub 10nm and such). There is a lot of fab for chips that do not require the latest and greatest. If LLMs make it easier / more accessible to design ASIC, I think those fabs will be the one who will benefit the most.
  1. aurareturn · 1790870894 · focus · HN ↗
    TSMC also dominates older fab nodes.
  2. thomasahle · 1790888090 · focus · HN ↗
    Yes, there's definitely a demand now for much faster to iterate manufacturing. Even at the cost of quality

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