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GPT-Synopsys: Frontier Intelligence to Revolutionize Chip Design

189 points · 111 comments · giuliomagnifico

  1. aniceperson · · focus · HN ↗
    > I see you are using Cadence IP in your project, unfortunately this is not allowed per the terms and conditions and you will be reported to the authorities

    Also : create proprietary locked down eda->no data to train models->models suck at it->reach out to ai lab to rl on it -> expect users to pay for eda and the model.

    1. DivingForGold · · focus · HN ↗
      ... > I see you are using Cadence IP in your project, unfortunately this is not allowed per the terms and conditions and you will be reported to the authorities

      EXACTLY, prepare to self deport immediately, push <proceed> to execute

      1. throwawaysnps · · focus · HN ↗
        ** Disclaimer: I work for Synopsys. **

        We also distribute Cadence IP. I know, crazy.

        1. not2b · · focus · HN ↗
          Also the other way around (Cadence shipping Synopsys IP). Big chips wind up with IP blocks from many sources and (at least usually) the right people get paid. And EDA engineers bounce around between Cadence, Synopsys, and Mentor (now Siemens EDA).
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