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Samsung is expected to more than double output of its HBM4 and HBM4E DRAM

562 points · 458 comments · giuliomagnifico

  1. fooker · · focus · HN ↗
    What's the main blocker (other than the current inflated cost) for using HBM instead of DRAM as the primary memory for consumer electronics?
    1. phkahler · · focus · HN ↗
      >> What's the main blocker (other than the current inflated cost) for using HBM instead of DRAM as the primary memory for consumer electronics?

      HBM is meant to be integrated into the same package as the CPU, so no more DIMM sockets. It also has higher latency apparently.

      1. MarleTangible · · focus · HN ↗
        One of the comments mentioned that they have a bus size of 2048, which may be why the latency is higher.

        > These chips have a massive bus size of 2048 bits, instead of the 64 or 128 bits (dual channel) used by DDR5.

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