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Samsung is expected to more than double output of its HBM4 and HBM4E DRAM

562 points · 458 comments · giuliomagnifico

  1. fooker · · focus · HN ↗
    What's the main blocker (other than the current inflated cost) for using HBM instead of DRAM as the primary memory for consumer electronics?
    1. bob1029 · · focus · HN ↗
      It's not that there's a blocker. It's that it takes roughly 3x the manufacturing capacity to produce an HBM package at the same storage capacity as DRAM. We are sacrificing total bytes for bandwidth.
      1. tliltocatl · · focus · HN ↗
        How so? FEOL is pretty much the same, BEOL is almost the same save TSVs, the packaging tech is different and more advanced, but not exactly 1:1 comparable. Do TSVs really occupy 3x the area of DDR IO's?
        1. Const-me · · focus · HN ↗
          See remark on the slide 11: <a href="https:&#x2F;&#x2F;www.servethehome.com&#x2F;micron-evolving-memory-architectures-for-ai-at-hot-chips-2026&#x2F;" rel="nofollow">https:&#x2F;&#x2F;www.servethehome.com&#x2F;micron-evolving-memory-architec... That presentation is by Micron.
          1. Karliss · · focus · HN ↗
            It doesn&#x27;t really say that it needs to use 3x more area, but that 3x more gets consumed due to &quot;advanced packaging and manfuacturing complexity&quot;. Which doesn&#x27;t properly explain why it consumes 3x more and could simply mean they have a bad yield and 2&#x2F;3 produced is garbage.
            1. bob1029 · · focus · HN ↗
              &gt; 2&#x2F;3 produced is garbage.

              This might not be far off the mark. You are irreversibly linking the fates of these devices after a certain stage of manufacturing. If something goes wrong at final packaging time, you lose all dies instead of one.

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