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How OpenAI Used Its Own LLMs to Design Its Jalapeño Chip

206 points · 139 comments · maxall4

  1. pama · · focus · HN ↗
    Having worked with people doing bringup of specialized chips, I am awed at how the world has changed.

    > When the first chips came back from the foundry in May, the team pointed its internal AI models at designing software to run benchmarks such as SemiAnalysis’s InferenceX. On DeepSeek’s multi-head latent attention kernel benchmark, performance climbed from 0.31 percent of the theoretical ceiling (set by the chip’s compute and memory bandwidth) to 88.94 percent in roughly 40 hours. Ho says this result is repeatable, so the time between when foundries deliver the first chips and when production ramps up can be reduced. “All our schedule assumptions are going to be based on the fact we have this capability now,” he says.

    1. wmf · · focus · HN ↗
      Back in the day you'd write the code before the chip came back but I guess today it's faster to wait.
      1. brookst · · focus · HN ↗
        Makes me wonder about AI and FPGAs. If the cost and effort to (re)program them goes to zero, maybe interesting new applications?
        1. UncleOxidant · · focus · HN ↗
          I've got some Tang nano and Tang primer boards (9k, 20k and 25k LUTs). The 9K has a cute little SPI LCD display. Claude has been able to interface with the boards via USB (it setup a UART on the FPGA to do so). We've gotten a GoL as well as a Pong game (where paddles are controlled by Tsetlin machines) and a MicroCNN that does MNIST classification. For the latter we were having trouble getting correct answers back from the CNN (accuracy was very poor which didn't match simulation). Claude created an on-chip logic analyzer and doggedly troubleshot the problem (turned out to be some kind of problem in the yosys synthesis tool - we had to use -noalu to work around). Anyway, I was blown away by this. Claude was communicating with the FPGA board and analyzing the data coming back from the internal logic analyzer.
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