Thread

1. taolson · 1786026262 · focus · HN ↗

   Wow, blast from the past! I was on the architecture / micro-architecture team for the 29K and 29050, and your story of writing and debugging the emulator brought up similar memories of working on the performance simulator for these chips.

   Very impressive work -- congratulations!

   1. nanochess · 1786039533 · focus · HN ↗

      Wow! Thank you! The floating-point implementation in the Am29050 is really great as it ran in parallel with the integer unit. Sorry, I need to ask, maybe you don't remember. What happens if you write into gr2-gr63? Not really needed to know, but I've been curious the last 30 years.

      1. taolson · 1786043673 · focus · HN ↗

         The FPU in the 29050 was pretty much a copy of the Am29325 bit-slice family FPU; an extra write port was added to the register file to allow for asynchronous FPU result writeback, which allowed the parallel operation.

         gr2 and gr3 were used in the 29050 for FP condition code registers, but otherwise I'm pretty sure accessing the rest caused a trap.

         1. nanochess · 1786046862 · focus · HN ↗

            Amazing! I didn't knew about the gr2 and gr3 register. I just searched for these in the user's manual, very sparse documentation. Thank you!

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